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Journals
Rallis K, Dimitrakis P, Karafyllidis I G, Rubio A, Sirakoulis G Ch
Electronic Properties of Graphene Nanoribbons With Defects Journal Article
In: IEEE Transactions on Nanotechnology, vol. 20, pp. 151–160, 2021.
@article{rallis2021electronic,
title = {Electronic Properties of Graphene Nanoribbons With Defects},
author = {Konstantinos Rallis and Panagiotis Dimitrakis and Ioannis G Karafyllidis and Antonio Rubio and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/document/9337210},
doi = {10.1109/TNANO.2021.3055135},
year = {2021},
date = {2021-01-27},
urldate = {2021-01-27},
journal = {IEEE Transactions on Nanotechnology},
volume = {20},
pages = {151--160},
publisher = {IEEE},
abstract = {Graphene nanoribbons (GNRs) are the most important emerging Graphene structures for nanoelectronic and sensor applications. GNRs with perfect lattices have been extensively studied, but fabricated GNRs contain lattice defects the effect of which on their electronic properties has not been studied extensively enough. In this paper, we apply the Non-Equilibrium Green's function (NEGF) method combined with tight-binding Hamiltonians to investigate the effect of lattice defects on the conductance of GNRs. We specifically study, butterfly shaped GNRs, which operate effectively as switches, and have been used in CMOS-like architectures. The cases of the most usual defects, namely the single and double vacancy have been analytically examined. The effect of these vacancies was computed by placing them in different regions and with various numbers on GNR nano-devices, namely edges, main body, contacts and narrow regions. The computation results are presented in the form of energy dispersion diagrams as well as diagrams of maximum conductance as a function of the number of lattice defects. We also present results on the defect tolerance of the butterfly shaped GNR devices.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Conferences
Rallis K, Dimitrakis P, Sirakoulis G Ch, Karafyllidis I, Rubio A
Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Proceedings Article
In: 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 97–98, IEEE 2020.
@inproceedings{rallis2020effect,
title = {Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon},
author = {Konstantinos Rallis and Panagiotis Dimitrakis and Georgios Ch. Sirakoulis and Ioannis Karafyllidis and Antonio Rubio},
url = {https://ieeexplore.ieee.org/document/9073648},
doi = {10.1109/NANOARCH47378.2019.181307},
year = {2020},
date = {2020-04-30},
urldate = {2020-01-01},
booktitle = {2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
pages = {97--98},
organization = {IEEE},
abstract = {Graphene nanoribbons are the most emerging graphene structures for electronic applications. Here, we present our calculation results on the impact of lattice defects on the transport properties of these structures. Preliminary results indicate that the maximum conductance is reduced significantly while the conductance quantization is lost even for a small number of defects.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Rallis K, Sirakoulis G Ch, Karafyllidis I, Rubio A
Multi-valued logic circuits on graphene quantum point contact devices Proceedings Article
In: NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, pp. 44–48, ACM ACM, 2018.
@inproceedings{rallis2018multi,
title = {Multi-valued logic circuits on graphene quantum point contact devices},
author = {Konstantinos Rallis and Georgios Ch. Sirakoulis and Ioannis Karafyllidis and Antonio Rubio},
url = {https://dl.acm.org/doi/10.1145/3232195.3232214},
doi = {doi.org/10.1145/3232195.3232214},
year = {2018},
date = {2018-07-17},
urldate = {2019-01-10},
booktitle = {NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures},
pages = {44--48},
publisher = {ACM},
organization = {ACM},
abstract = {Graphene quantum point contacts (G-QPC) combine switching operations with quantized conductance, which can be modulated by top and back gates. Here we use the conductance quantization to design and simulate multi-valued logic (MVL) circuits and, more specifically an adder. The adder comprises two G-QPCs connected in parallel. We compute the conductance of the adder for various inputs and show that Graphene MVL circuits are feasible.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}