Mar 23

Reported by Dr. Phil Garrou, contributing editor, in ElectoIQ, 18 March 2011.

At the recent CeBIT Fair in Hanover, Germany, IBM CEO Sam Palmisano announced that IBM’s 3D technology will likely appear in its Power8 processor, planned for 2013, using 28nm or 22nm process technology.

The first goal, he indicated, is to place the memory directly above or beneath the CPU. The processor will likely employ a linked memory and “a layer of small specialized computing cores adapted for specific intended uses.” Future plans envision up to 100,000 connections per mm2 in silicon.

The principal issue with 3D ICs for processor units is cooling. IBM has undertaken 3D stack cooling research with the École Polytechnique Federale and ETH Zurich. At the CeBIT fair, IBM scientists presented the first test chips in which cooling water is circulated through 50µm channels (i.e microchannel cooling). Bruno Michel, manager of the Advanced Thermal Packaging group at IBM Research Zurich, reported that the energy-efficient hot water-cooling technology is part of their concept of a zero-emission data center. 3D chip stacks which generate more heat than a single processor, in almost the same amount of space, are cooled using water and not air to reduce energy consumption. IBM reports that it will be a few more years before this technology is ready for production.

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