Books
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Book Chapters
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Editorials
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Journals
7.
Vasileiadis N, Ntinas V, Karakolis P, Dimitrakis P, Sirakoulis G C
On Edge Image Processing Acceleration with Low Power Neuro-Memristive Segmented Crossbar Array Architecture. Journal Article
In: International Journal of Unconventional Computing, vol. 17, no. 3, 2022.
@article{vasileiadis2022edge,
title = {On Edge Image Processing Acceleration with Low Power Neuro-Memristive Segmented Crossbar Array Architecture.},
author = {Nikolaos Vasileiadis and Vasileios Ntinas and Panagiotis Karakolis and Panagiotis Dimitrakis and Georgios Ch Sirakoulis},
year = {2022},
date = {2022-01-01},
journal = {International Journal of Unconventional Computing},
volume = {17},
number = {3},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
6.
Mavropoulis A, Vasileiadis N, Theodorou C, Sygellou L, Normand P, Sirakoulis G C, Dimitrakis P
Effect of SOI substrate on silicon nitride resistance switching using MIS structure Journal Article
In: Solid-State Electronics, vol. 194, pp. 108375, 2022.
@article{mavropoulis2022effect,
title = {Effect of SOI substrate on silicon nitride resistance switching using MIS structure},
author = {A Mavropoulis and N Vasileiadis and C Theodorou and L Sygellou and P Normand and G Ch Sirakoulis and P Dimitrakis},
year = {2022},
date = {2022-01-01},
journal = {Solid-State Electronics},
volume = {194},
pages = {108375},
publisher = {Elsevier},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
5.
Fyrigos I, Ntinas V, Vasileiadis N, Sirakoulis G Ch, Dimitrakis P, Zhang Y, Karafyllidis I G
Memristor Crossbar Arrays Performing Quantum Algorithms Journal Article Forthcoming
In: IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1-12, Forthcoming.
@article{fyrigos2021memristorb,
title = {Memristor Crossbar Arrays Performing Quantum Algorithms},
author = {Iosif-Angelos Fyrigos and Vasileios Ntinas and Nikolaos Vasileiadis and Georgios Ch. Sirakoulis and Panagiotis Dimitrakis and Yue Zhang and Ioannis G Karafyllidis},
url = {https://ieeexplore.ieee.org/document/9610620},
doi = {10.1109/TCSI.2021.3123575},
year = {2021},
date = {2021-11-13},
urldate = {2021-11-13},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
pages = {1-12},
publisher = {IEEE},
abstract = {There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today's classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm.},
keywords = {},
pubstate = {forthcoming},
tppubtype = {article}
}
There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today's classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm.
4.
Vasileiadis N, Loukas P, Karakolis P, Ioannou-Sougleridis V, Normand P, Ntinas V, Fyrigos I, Karafyllidis I, Sirakoulis G Ch, Dimitrakis P
Multi-level resistance switching and random telegraph noise analysis of nitride based memristors Journal Article
In: Chaos, Solitons & Fractals, vol. 153, no. 1, pp. 11153, 2021.
@article{vasileiadis2021multi,
title = {Multi-level resistance switching and random telegraph noise analysis of nitride based memristors},
author = {Nikolaos Vasileiadis and Panagiotis Loukas and Panagiotis Karakolis and Vassilios Ioannou-Sougleridis and Pascal Normand and Vasileios Ntinas and Iosif-Angelos Fyrigos and Ioannis Karafyllidis and Georgios Ch. Sirakoulis and Panagiotis Dimitrakis},
url = {https://www.sciencedirect.com/science/article/abs/pii/S0960077921008870},
doi = {doi.org/10.1016/j.chaos.2021.111533},
year = {2021},
date = {2021-11-11},
urldate = {2021-01-01},
journal = {Chaos, Solitons \& Fractals},
volume = {153},
number = {1},
pages = {11153},
publisher = {Elsevier},
abstract = {Resistance switching devices are of special importance because of their application in resistive memories (RRAM) which are promising candidates for replacing current nonvolatile memories and realize storage class memories. These devices exhibit usually memristive properties with many discrete resistance levels and implement artificial synapses. The last years, researchers have demonstrated memristive chips as accelerators in computing, following new in-memory and neuromorphic computational approaches. Many different metal oxides have been used as resistance switching materials in MIM or MIS structures. Understanding of the mechanism and the dynamics of resistance switching is very critical for the modeling and use of memristors in different applications. Here, we demonstrate the bipolar resistance switching of silicon nitride thin films using heavily doped Si and Cu as bottom and top-electrodes, respectively. Analysis of the current-voltage characteristics reveal that under space-charge limited conditions and appropriate current compliance setting, multi-level resistance operation can be achieved. Furthermore, a flexible tuning protocol for multi-level resistance switching was developed applying appropriate SET/RESET pulse sequences. Retention and random telegraph noise measurements performed at different resistance levels. The present results reveal the attractive properties of the examined devices.
},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Resistance switching devices are of special importance because of their application in resistive memories (RRAM) which are promising candidates for replacing current nonvolatile memories and realize storage class memories. These devices exhibit usually memristive properties with many discrete resistance levels and implement artificial synapses. The last years, researchers have demonstrated memristive chips as accelerators in computing, following new in-memory and neuromorphic computational approaches. Many different metal oxides have been used as resistance switching materials in MIM or MIS structures. Understanding of the mechanism and the dynamics of resistance switching is very critical for the modeling and use of memristors in different applications. Here, we demonstrate the bipolar resistance switching of silicon nitride thin films using heavily doped Si and Cu as bottom and top-electrodes, respectively. Analysis of the current-voltage characteristics reveal that under space-charge limited conditions and appropriate current compliance setting, multi-level resistance operation can be achieved. Furthermore, a flexible tuning protocol for multi-level resistance switching was developed applying appropriate SET/RESET pulse sequences. Retention and random telegraph noise measurements performed at different resistance levels. The present results reveal the attractive properties of the examined devices.
3.
Vasileiadis N, Ntinas V, Sirakoulis G Ch, Dimitrakis P
In-Memory-Computing Realization with a Photodiode/Memristor Based Vision Sensor Journal Article
In: Materials, vol. 14, no. 18, pp. 5223, 2021.
@article{vasileiadis2021memory,
title = {In-Memory-Computing Realization with a Photodiode/Memristor Based Vision Sensor},
author = {Nikolaos Vasileiadis and Vasileios Ntinas and Georgios Ch. Sirakoulis and Panagiotis Dimitrakis},
url = {https://www.mdpi.com/1996-1944/14/18/5223},
doi = {doi.org/10.3390/ma14185223},
year = {2021},
date = {2021-09-10},
urldate = {2021-09-10},
journal = {Materials},
volume = {14},
number = {18},
pages = {5223},
publisher = {Multidisciplinary Digital Publishing Institute},
abstract = {State-of-the-art IoT technologies request novel design solutions in edge computing, resulting in even more portable and energy-efficient hardware for in-the-field processing tasks. Vision sensors, processors, and hardware accelerators are among the most demanding IoT applications. Resistance switching (RS) two-terminal devices are suitable for resistive RAMs (RRAM), a promising technology to realize storage class memories. Furthermore, due to their memristive nature, RRAMs are appropriate candidates for in-memory computing architectures. Recently, we demonstrated a CMOS compatible silicon nitride (SiNx) MIS RS device with memristive properties. In this paper, a report on a new photodiode-based vision sensor architecture with in-memory computing capability, relying on memristive device, is disclosed. In this context, the resistance switching dynamics of our memristive device were measured and a data-fitted behavioral model was extracted. SPICE simulations were made highlighting the in-memory computing capabilities of the proposed photodiode-one memristor pixel vision sensor. Finally, an integration and manufacturing perspective was discussed.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
State-of-the-art IoT technologies request novel design solutions in edge computing, resulting in even more portable and energy-efficient hardware for in-the-field processing tasks. Vision sensors, processors, and hardware accelerators are among the most demanding IoT applications. Resistance switching (RS) two-terminal devices are suitable for resistive RAMs (RRAM), a promising technology to realize storage class memories. Furthermore, due to their memristive nature, RRAMs are appropriate candidates for in-memory computing architectures. Recently, we demonstrated a CMOS compatible silicon nitride (SiNx) MIS RS device with memristive properties. In this paper, a report on a new photodiode-based vision sensor architecture with in-memory computing capability, relying on memristive device, is disclosed. In this context, the resistance switching dynamics of our memristive device were measured and a data-fitted behavioral model was extracted. SPICE simulations were made highlighting the in-memory computing capabilities of the proposed photodiode-one memristor pixel vision sensor. Finally, an integration and manufacturing perspective was discussed.
2.
Vasileiadis N, Karakolis P, Mandylas P, Ioannou-Sougleridis V, Normand P, Perego M, Komninou P, Ntinas V, Fyrigos I, Karafyllidis I, Sirakoulis G Ch, Dimitrakis P
Understanding the role of defects in silicon nitride-based resistive switching memories through oxygen doping Journal Article
In: IEEE Transactions on Nanotechnology, vol. 20, pp. 356–364, 2021.
@article{vasileiadis2021understanding,
title = {Understanding the role of defects in silicon nitride-based resistive switching memories through oxygen doping},
author = {Nikolaos Vasileiadis and Panagiotis Karakolis and Panagiotis Mandylas and Vassilios Ioannou-Sougleridis and Pascal Normand and Michele Perego and Philomela Komninou and Vasileios Ntinas and Iosif-Angelos Fyrigos and Ioannis Karafyllidis and Georgios Ch. Sirakoulis and Panagiotis Dimitrakis},
url = {https://ieeexplore.ieee.org/document/9403953},
doi = {10.1109/TNANO.2021.3072974},
year = {2021},
date = {2021-04-13},
urldate = {2021-01-01},
journal = {IEEE Transactions on Nanotechnology},
volume = {20},
pages = {356--364},
publisher = {IEEE},
abstract = {Resistive memories are promising candidates for replacing current nonvolatile memories and realize storage class memories. Moreover, they have memristive properties, with many discrete resistance levels and implement artificial synapses. The last years researchers have demonstrated RRAM chips used as accelerators in computing, following the new in-memory and neuromorphic computational approaches. Many different metal oxides have been used as resistance switching materials in MIM structures. Understanding of the switching mechanism is very critical for the modeling and the use of memristors in different applications. Here, we demonstrate the bipolar resistance switching of silicon nitride thin films using heavily doped Si and Cu as bottom and top-electrodes respectively. Next, we dope nitride with oxygen in order to introduce and modify the intrinsic nitride defects. Analysis of the current-voltage characteristics reveal that under space-charge limited conditions and by setting the appropriate current compliance, the operation condition of the RRAM cells can be tuned. Furthermore, resistance change can be obtained using appropriate SET/RESET pulsing sequences allowing the use of the devices in computing acceleration application. Impedance spectroscopy measurements clarify the presence of different mechanisms during SET and RESET. We prove through a customized measurement set-up and the appropriate control software that the initial charge-storage in the intrinsic nitride traps governs the resistance change.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Resistive memories are promising candidates for replacing current nonvolatile memories and realize storage class memories. Moreover, they have memristive properties, with many discrete resistance levels and implement artificial synapses. The last years researchers have demonstrated RRAM chips used as accelerators in computing, following the new in-memory and neuromorphic computational approaches. Many different metal oxides have been used as resistance switching materials in MIM structures. Understanding of the switching mechanism is very critical for the modeling and the use of memristors in different applications. Here, we demonstrate the bipolar resistance switching of silicon nitride thin films using heavily doped Si and Cu as bottom and top-electrodes respectively. Next, we dope nitride with oxygen in order to introduce and modify the intrinsic nitride defects. Analysis of the current-voltage characteristics reveal that under space-charge limited conditions and by setting the appropriate current compliance, the operation condition of the RRAM cells can be tuned. Furthermore, resistance change can be obtained using appropriate SET/RESET pulsing sequences allowing the use of the devices in computing acceleration application. Impedance spectroscopy measurements clarify the presence of different mechanisms during SET and RESET. We prove through a customized measurement set-up and the appropriate control software that the initial charge-storage in the intrinsic nitride traps governs the resistance change.
1.
Papandroulidakis G, Vourkas I, Vasileiadis N, Sirakoulis G Ch
Boolean Logic Operations and Computing Circuits Based on Memristors Journal Article
In: IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 12, pp. 972–975, 2014.
@article{papandroulidakis2014boolean,
title = {Boolean Logic Operations and Computing Circuits Based on Memristors},
author = {Georgios Papandroulidakis and Ioannis Vourkas and Nikolaos Vasileiadis and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/document/6895305},
doi = {10.1109/TCSII.2014.2357351},
year = {2014},
date = {2014-09-11},
urldate = {2014-01-01},
journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
volume = {61},
number = {12},
pages = {972--975},
publisher = {IEEE},
abstract = {This brief contributes to the design of computational and reconfigurable structures that exploit unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation-based validation of the proposed circuits and systems is provided.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
This brief contributes to the design of computational and reconfigurable structures that exploit unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation-based validation of the proposed circuits and systems is provided.
Conferences
7.
Tsakalos , Karolos-Alexandros , Ntinas V, Karamani R, Fyrigos I, Chatzinikolaou T P, Vasileiadis N, Dimitrakis P, Provata A, Sirakoulis G Ch
Emergence of Chimera States with Re-programmable Memristor Crossbar Arrays Proceedings Article
In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, IEEE 2021.
@inproceedings{tsakalos2021emergence,
title = {Emergence of Chimera States with Re-programmable Memristor Crossbar Arrays},
author = {Tsakalos and Karolos-Alexandros and Vasileios Ntinas and Rafailia-Eleni Karamani and Iosif-Angelos Fyrigos and Theodoros Panagiotis Chatzinikolaou and Nikolaos Vasileiadis and Panagiotis Dimitrakis and Astero Provata and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/document/9401669},
doi = {10.1109/ISCAS51556.2021.9401669},
year = {2021},
date = {2021-04-27},
urldate = {2021-01-01},
booktitle = {2021 IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1--5},
organization = {IEEE},
abstract = {The time series of the brain are usually characterized by the co-existence of synchronized and desynchronized behaviors. This kind of behavior is related to normal and disorderly functions of the brain. One of the suggested mechanisms to understand thoroughly this behavior are chimera states, which are characterized by the coincidence of coherent and incoherent dynamics that can be exploited through networks of symmetrically coupled identical oscillators. In this work, ring-based networks of Chua's circuits, the simplest electronic oscillators that perform chaotic and well-known bifurcation phenomena, have been extensively studied in memristive crossbars (Xbar), revealing various collective spatio-temporal behaviors, such as chimera states. With respect to different Xbar connectivities and via SPICE-level circuit simulations, the proposed Xbar system proves its efficacy to reproduce spatio-temporal patterns spanning from complete synchronization and chimera states up to fully chaotic states.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The time series of the brain are usually characterized by the co-existence of synchronized and desynchronized behaviors. This kind of behavior is related to normal and disorderly functions of the brain. One of the suggested mechanisms to understand thoroughly this behavior are chimera states, which are characterized by the coincidence of coherent and incoherent dynamics that can be exploited through networks of symmetrically coupled identical oscillators. In this work, ring-based networks of Chua's circuits, the simplest electronic oscillators that perform chaotic and well-known bifurcation phenomena, have been extensively studied in memristive crossbars (Xbar), revealing various collective spatio-temporal behaviors, such as chimera states. With respect to different Xbar connectivities and via SPICE-level circuit simulations, the proposed Xbar system proves its efficacy to reproduce spatio-temporal patterns spanning from complete synchronization and chimera states up to fully chaotic states.
6.
Vasileiadis N, Ntinas V, Fyrigos I, Karamani R, Ioannou-Sougleridis V, Normand P, Karafyllidis I, Sirakoulis G Ch, Dimitrakis P
A new 1P1R Image Sensor with In-Memory Computing Properties based on Silicon Nitride Devices Proceedings Article
In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, IEEE IEEE, 2021.
@inproceedings{vasileiadis2021new,
title = {A new 1P1R Image Sensor with In-Memory Computing Properties based on Silicon Nitride Devices},
author = {Nikolaos Vasileiadis and Vasileios Ntinas and Iosif-Angelos Fyrigos and Rafailia-Eleni Karamani and Vassilios Ioannou-Sougleridis and Pascal Normand and Ioannis Karafyllidis and Georgios Ch. Sirakoulis and Panagiotis Dimitrakis},
url = {https://ieeexplore.ieee.org/abstract/document/9401586},
doi = {10.1109/ISCAS51556.2021.9401586},
year = {2021},
date = {2021-04-27},
urldate = {2021-04-27},
booktitle = {2021 IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1--5},
publisher = {IEEE},
organization = {IEEE},
abstract = {Research progress in edge computing hardware, capable of demanding in-the-field processing tasks with simultaneous memory and low power properties, is leading the way towards a revolution in IoT hardware technology. Resistive random access memories (RRAM) are promising candidates for replacing current non-volatile memories and realize storage class memories, but also due to their memristive nature they are the perfect candidates for in-memory computing architectures. In this context, a CMOS compatible silicon nitride (SiN) device with memristive properties is presented accompanied by a data-fitted model extracted through analysis of measured resistance switching dynamics. Additionally, a new phototransistor-based image sensor architecture with integrated SiN memristor (1P1R) was presented. The in-memory computing capabilities of the 1P1R device were evaluated through SPICE-level circuit simulation with the previous presented device model. Finally, the fabrication aspects of the sensor are discussed.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Research progress in edge computing hardware, capable of demanding in-the-field processing tasks with simultaneous memory and low power properties, is leading the way towards a revolution in IoT hardware technology. Resistive random access memories (RRAM) are promising candidates for replacing current non-volatile memories and realize storage class memories, but also due to their memristive nature they are the perfect candidates for in-memory computing architectures. In this context, a CMOS compatible silicon nitride (SiN) device with memristive properties is presented accompanied by a data-fitted model extracted through analysis of measured resistance switching dynamics. Additionally, a new phototransistor-based image sensor architecture with integrated SiN memristor (1P1R) was presented. The in-memory computing capabilities of the 1P1R device were evaluated through SPICE-level circuit simulation with the previous presented device model. Finally, the fabrication aspects of the sensor are discussed.
5.
Fyrigos I, Chatzinikolaou T P, Ntinas V, Vasileiadis N, Dimitrakis P, Karafyllidis I, Sirakoulis G Ch
Memristor Crossbar Design Framework for Quantum Computing Proceedings Article
In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, IEEE 2021, ISBN: 978-1-7281-9201-7.
@inproceedings{fyrigos2021memristor,
title = {Memristor Crossbar Design Framework for Quantum Computing},
author = {Iosif-Angelos Fyrigos and Theodoros Panagiotis Chatzinikolaou and Vasileios Ntinas and Nikolaos Vasileiadis and Panagiotis Dimitrakis and Ioannis Karafyllidis and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/document/9401581},
doi = {10.1109/ISCAS51556.2021.9401581},
isbn = {978-1-7281-9201-7},
year = {2021},
date = {2021-04-27},
urldate = {2021-01-01},
booktitle = {2021 IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1--5},
organization = {IEEE},
abstract = {Over the last years there has been significant progress in the development of quantum computers. It has been demonstrated that they can accelerate the solution of various problems exponentially compared to today's classical computers, harnessing the properties of superposition and entanglement, two resources that have no classical analog. Since quantum computer platforms that are currently available comprise only a few tenths of qubits, as well as the access to a fabricated quantum computer is time limited for the majority of researchers, the use of quantum simulators is essential in developing and testing new quantum algorithms. Taking inspiration from previous work on developing a novel quantum simulator based on memristor crossbar circuits, in this work, a framework that automates the circuit design of emulated quantum gates is presented. The proposed design framework deals with the generation and programming of memristor crossbar configuration that incorporates the desirable quantum circuit, leading to a technology agnostic design tool. To such a degree, various quantum gates can be efficiently emulated on memristor crossbar configurations for various types of memristive devices, aiming to assist and accelerate the fabrication process of a memristor based quantum simulator.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Over the last years there has been significant progress in the development of quantum computers. It has been demonstrated that they can accelerate the solution of various problems exponentially compared to today's classical computers, harnessing the properties of superposition and entanglement, two resources that have no classical analog. Since quantum computer platforms that are currently available comprise only a few tenths of qubits, as well as the access to a fabricated quantum computer is time limited for the majority of researchers, the use of quantum simulators is essential in developing and testing new quantum algorithms. Taking inspiration from previous work on developing a novel quantum simulator based on memristor crossbar circuits, in this work, a framework that automates the circuit design of emulated quantum gates is presented. The proposed design framework deals with the generation and programming of memristor crossbar configuration that incorporates the desirable quantum circuit, leading to a technology agnostic design tool. To such a degree, various quantum gates can be efficiently emulated on memristor crossbar configurations for various types of memristive devices, aiming to assist and accelerate the fabrication process of a memristor based quantum simulator.
4.
Vasileiadis N, Dimitrakis P, Ntinas V, Sirakoulis G Ch
True Random Number Generator Based on Multi-State Silicon Nitride Memristor Entropy Sources Combination Proceedings Article
In: 2021 International Conference on Electronics, Information, and Communication (ICEIC), pp. 1–4, IEEE 2021.
@inproceedings{vasileiadis2021true,
title = {True Random Number Generator Based on Multi-State Silicon Nitride Memristor Entropy Sources Combination},
author = {Nikolaos Vasileiadis and Panagiotis Dimitrakis and Vasileios Ntinas and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/document/9369817},
doi = {10.1109/ICEIC51217.2021.9369817},
year = {2021},
date = {2021-03-10},
urldate = {2021-03-10},
booktitle = {2021 International Conference on Electronics, Information, and Communication (ICEIC)},
pages = {1--4},
organization = {IEEE},
abstract = {True random number generators (TRNG) are key components in information security systems. Moreover, in the era of the internet of things (IoT), the demands on smaller, faster, simpler and more power efficient TRGN circuits increased. Meeting these requirements, resistance switching devices, used also as resistive memory cells (ReRAMs), are attractive candidates to implement entropy sources due to their inherent stochasticity. In this work, we present a novel design of TRNG hardware based on a silicon nitride memristor. Multi-state currents are utilized as different entropy sources increasing the overall entropy of the circuit. A post-processing of the generated bitstreams was made with a simple Xorshift combinational logic circuit. The robustness of the proposed design is verified with NIST randomness tests.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
True random number generators (TRNG) are key components in information security systems. Moreover, in the era of the internet of things (IoT), the demands on smaller, faster, simpler and more power efficient TRGN circuits increased. Meeting these requirements, resistance switching devices, used also as resistive memory cells (ReRAMs), are attractive candidates to implement entropy sources due to their inherent stochasticity. In this work, we present a novel design of TRNG hardware based on a silicon nitride memristor. Multi-state currents are utilized as different entropy sources increasing the overall entropy of the circuit. A post-processing of the generated bitstreams was made with a simple Xorshift combinational logic circuit. The robustness of the proposed design is verified with NIST randomness tests.
3.
Ntinas V, Karamani R, Fyrigos I, Vasileiadis N, Stathis D, Vourkas I, Dimitrakis P, Karafyllidis I, Sirakoulis G Ch
Cellular Automata coupled with Memristor devices: A fine unconventional computing paradigm Proceedings Article
In: 2020 International Conference on Electronics, Information, and Communication (ICEIC), pp. 1–4, IEEE IEEE, 2020.
@inproceedings{ntinas2020cellular,
title = {Cellular Automata coupled with Memristor devices: A fine unconventional computing paradigm},
author = {Vasileios Ntinas and Rafailia-Eleni Karamani and Iosif-Angelos Fyrigos and Nikolaos Vasileiadis and Dimitrios Stathis and Ioannis Vourkas and Panagiotis Dimitrakis and Ioannis Karafyllidis and Georgios Ch. Sirakoulis},
url = {https://ieeexplore.ieee.org/abstract/document/9051236},
doi = {10.1109/ICEIC49074.2020.9051236},
year = {2020},
date = {2020-04-02},
urldate = {2020-04-02},
booktitle = {2020 International Conference on Electronics, Information, and Communication (ICEIC)},
pages = {1--4},
publisher = {IEEE},
organization = {IEEE},
abstract = {Cellular Automata (CAs), a ubiquitous computational tool proposed by John von Neumann, illustrate how great complexity emerges from simple rules of dynamical transitions between space and time interconnected simplistic entities. CAs perform as mathematical computation models, but also they are a powerful medium to model nature and natural systems. As a computational platform, CAs come with unified memory and computation in the same physical area, attributed as a strong candidate against the limitations of data transfer, known as the von Neumann bottleneck. On the other hand, Memristors with their inherent Computing-In-Memory compatibility, can be easily considered as appropriate nanoelectronic devices to be coupled with CAs towards an energy and time efficient computational paradigm. In particular, CA present a vast area of applications, comprising various NP-complete hard to be solved problems arriving from computer science field, like the well-known Shortest Path, Bin Packing, Knapsack and Max-clique problems, as well as physical, chemical and biological processes and phenomena, such as epileptic seizures in relation with healthy and pathogenic brain regions and, moreover, real life applications like pseudorandom number generation and simplistic, but with highly complex behavior, models like the famous Game of Life. The outcome of employing Memristors in CAs applications is promising in terms of parallelization, power consumption, scalability, reconfigurability, and high computing performance.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Cellular Automata (CAs), a ubiquitous computational tool proposed by John von Neumann, illustrate how great complexity emerges from simple rules of dynamical transitions between space and time interconnected simplistic entities. CAs perform as mathematical computation models, but also they are a powerful medium to model nature and natural systems. As a computational platform, CAs come with unified memory and computation in the same physical area, attributed as a strong candidate against the limitations of data transfer, known as the von Neumann bottleneck. On the other hand, Memristors with their inherent Computing-In-Memory compatibility, can be easily considered as appropriate nanoelectronic devices to be coupled with CAs towards an energy and time efficient computational paradigm. In particular, CA present a vast area of applications, comprising various NP-complete hard to be solved problems arriving from computer science field, like the well-known Shortest Path, Bin Packing, Knapsack and Max-clique problems, as well as physical, chemical and biological processes and phenomena, such as epileptic seizures in relation with healthy and pathogenic brain regions and, moreover, real life applications like pseudorandom number generation and simplistic, but with highly complex behavior, models like the famous Game of Life. The outcome of employing Memristors in CAs applications is promising in terms of parallelization, power consumption, scalability, reconfigurability, and high computing performance.
2.
Vourkas I, Gómez J, Abusleme Á, Vasileiadis N, Sirakoulis G Ch, Rubio A
Exploring the voltage divider approach for accurate memristor state tuning Proceedings Article
In: 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1–4, IEEE IEEE, 2017.
@inproceedings{vourkas2017exploring,
title = {Exploring the voltage divider approach for accurate memristor state tuning},
author = {Ioannis Vourkas and Jorge G\'{o}mez and \'{A}ngel Abusleme and Nikolaos Vasileiadis and Georgios Ch. Sirakoulis and Antonio Rubio},
url = {https://ieeexplore.ieee.org/document/7948043},
doi = {10.1109/LASCAS.2017.7948043},
year = {2017},
date = {2017-06-15},
urldate = {2017-01-01},
booktitle = {2017 IEEE 8th Latin American Symposium on Circuits \& Systems (LASCAS)},
pages = {1--4},
publisher = {IEEE},
organization = {IEEE},
abstract = {The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multi-level programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve \<;1% tuning precision, on average 3x faster than another accurate tuning algorithm of the recent literature.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multi-level programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <;1% tuning precision, on average 3x faster than another accurate tuning algorithm of the recent literature.
1.
Vourkas I, Abusleme Á, Vasileiadis N, Sirakoulis G Ch, Papamarkos N
Towards memristive crossbar-based neuromorphic HW accelerators for signal processing Proceedings Article
In: 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST), pp. 1–4, IEEE IEEE, 2017.
@inproceedings{vourkas2017towards,
title = {Towards memristive crossbar-based neuromorphic HW accelerators for signal processing},
author = {I Vourkas and \'{A} Abusleme and N Vasileiadis and Georgios Ch. Sirakoulis and N Papamarkos},
url = {https://ieeexplore.ieee.org/document/7937678},
doi = {10.1109/MOCAST.2017.7937678},
year = {2017},
date = {2017-06-01},
urldate = {2017-06-01},
booktitle = {2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)},
pages = {1--4},
publisher = {IEEE},
organization = {IEEE},
abstract = {Research progress in neuromorphic hardware, capable of biological perception and cognitive information processing, is leading the way towards a revolution in computing technology. Current research efforts have focused mainly on resistive switching devices, the electronic analog of synapses in artificial neural networks (ANNs), and the crossbar nanoarchitecture, for its huge connectivity and maximum integration density. In this context, this work presents the design and simulation of a memristive crossbar-based ANN for text recognition tasks, implementing a novel computing algorithm. In such case study, important issues during the application mapping process are identified and properly addressed at device and circuit level. The computing capabilities of the proposed system are highlighted through SPICE-level circuit simulations, which show excellent agreement with theoretical simulation results.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Research progress in neuromorphic hardware, capable of biological perception and cognitive information processing, is leading the way towards a revolution in computing technology. Current research efforts have focused mainly on resistive switching devices, the electronic analog of synapses in artificial neural networks (ANNs), and the crossbar nanoarchitecture, for its huge connectivity and maximum integration density. In this context, this work presents the design and simulation of a memristive crossbar-based ANN for text recognition tasks, implementing a novel computing algorithm. In such case study, important issues during the application mapping process are identified and properly addressed at device and circuit level. The computing capabilities of the proposed system are highlighted through SPICE-level circuit simulations, which show excellent agreement with theoretical simulation results.